Session: 18-01-05: Conventional Manufacturing

Paper Number: 149328

149328 - Singulated Die Sort as a Tool to Enable High Precision Thermal Control During High-Volume Manufacturing 

Test of semiconductor devices at different stages of the manufacturing flow is a critical aspect during production for Foundries, as it ensures that components are meeting quality and performance requirements based on their market segment. The first step in the manufacturing flow after wafers are fabricated is to test them using a tool that sorts the dice to provide the first segregation of good and bad units. The test content that is used for this first screening causes heat to be generated by the silicon as different parts of the device are exercised to look for defects. The heat generated needs to be managed by the test equipment to ensure that the devices are maintained at a target set point defined based on product segment, while active content is executed in the silicon. Typical test patterns are dynamic in nature thus resulting in a highly fluctuating temperature response that needs to be compensated by a thermal controller. A tool to perform such testing is known as Wafer Sort, and it enables the testing multiple dice in parallel culminating in the selection of only the functional "good" die to be packaged, tested downstream and ultimately shipped to customers. As such, Sort serves as the first screen for die manufactured by the Fab. While critical for a wide variety of silicon architectures, Wafer Sort's main drawback is that it requires using massive metallic chucks to support full wafer dimensions. These massive chucks introduce lag in the system’s ability to respond to power and temperature fluctuations on the device under test that occur when test content is executed. The lack of thermal responsiveness of Wafer Sort chucks limits the type of content that can be applied at Sort, with the most power-intensive content shifting downstream to Burn-In, Class Test or System-Level Test all of which are done after package assembly. As heterogeneous integration, or disaggregation, gains importance as a means to drive Moore’s Law, there is a need to enable more aggressive test content at Sort to improve final packaged unit yield. In this presentation, we will discuss the advantages of Singulated Die Sort (SDx) in extending the Sort envelope to enable improved coverage to stress and screen defects on the silicon at the die and die stack level, while minimizing the need for test at the package level. While a general overview of the tools will be reviewed, this presentation will directly compare the thermal capabilities of Wafer Sort and Die Sort equipment, demonstrating the significant advantages of SDx.

Presenting Author: Jaime Sanchez Intel Corporation

Presenting Author Biography: Jaime Sanchez is a Technologist at Intel Corporation in Oregon and has over sixteen years of experience in design of test equipment for semiconductors, thermal analysis and experimentation. He has a Ph.D. in Mechanical Engineering from the University of Kentucky and is a licensed Professional Engineer. Since joining Intel, Jaime has worked in research and development for test equipment and thermal tools used in high volume manufacturing and silicon validation, as well as data center cooling solutions for high-end server products. He currently manages the Sort module development team where he leads the development of the next generation thermal technology for Sort. Jaime is also an adjunct faculty in Mechanical and Materials Engineering Department at Portland State University where he teaches Thermodynamics and Heat Transfer.

Authors:

Jaime Sanchez Intel Corporation