Session: 14-10-01: Micro/Nanofluidics 2025 I

Paper Number: 164908

Characterization of Probe Properties for Wafer Probing and Geometric Optimization of Multilayer Cantilever Probe Cards 

Probe cards are critical components in wafer-level testing, ensuring reliable electrical contact between test equipment and semiconductor devices. As integrated circuits (ICs) continue to evolve toward higher pin counts and greater integration density, multi-layer cantilever probe cards are increasingly utilized to accommodate these demands. However, the dense arrangement of probe needles introduces several challenges, including mechanical interference, variations in contact force, and inconsistent scrub marks on bond pads. These factors can impact test accuracy, device reliability, and long-term probe card performance. Therefore, optimizing the structural design of multi-layer probe cards is essential to achieving uniform contact performance and minimizing variations across layers.

This study employs a combined experimental and computational approach to investigate the dynamic deformation behavior of probe needles in a five-layer cantilever probe card. The mechanical properties of Rhenium-Tungsten (ReW) probe needles were characterized through tensile testing at varying temperatures and strain rates using an MTS-Acumen microforce tester. The resulting stress-strain curves were analyzed to develop empirical constitutive models that accurately capture the thermomechanical behavior of the probe material under operational conditions. These constitutive models were then integrated into a three-dimensional (3D) finite element model (FEM) to simulate the mechanical response of the probe card during wafer contact.

The FEM was validated by comparing the predicted contact forces of the five-layer probe card with experimental measurements obtained using a PRVX probe card inspection system. The validation results demonstrated strong agreement, confirming the model's ability to accurately represent probe deformation behavior and contact dynamics. The validated model was then used to systematically analyze the influence of key geometric parameters, including taper length, beam length, and bending angle, on scrub mark formation, contact force distribution, and probe alignment consistency.

To further optimize probe card performance, Castigliano’s second theorem was employed to derive analytical relationships between probe geometry and mechanical response. This analytical framework was then integrated with a multi-objective genetic algorithm (MOGA) to refine the design of the probe needles, with optimization objectives focused on achieving uniform scrub mark length, minimizing stress concentrations, and ensuring stable contact force distribution across all layers. The optimization process considered the trade-offs between mechanical compliance and contact reliability, ensuring that the probe card maintains its structural integrity while improving testing consistency.

The results indicate that adjusting the taper length and bending angle significantly enhances scrub mark uniformity, reducing variability across different probe layers and improving overall test accuracy. Specifically, an optimized combination of these parameters minimizes probe misalignment and wear on bond pads, ultimately enhancing the lifespan and reliability of the probe card. Furthermore, the study provides a systematic and repeatable methodology for probe card design optimization, applicable to a wide range of semiconductor testing environments.

The insights gained from this research contribute to the advancement of probe card design for next-generation wafer testing applications. The proposed framework can be extended to other multi-layer probe card configurations and integrated with additional material models to further improve testing efficiency and reliability. By bridging experimental material characterization with advanced computational modeling and optimization techniques, this study offers a valuable approach for improving semiconductor probe card performance in high-precision manufacturing environments.

Presenting Author: Mengkai Shih National Sun Yat-sen University, Department of Mechanical and Electro-Mechanical Engineering

Presenting Author Biography: Meng-Kai Shih received his Ph.D. degree in Mechanical Engineering from National Chung Cheng University, Chiayi, Taiwan, in 2006. He is currently an Assistant Professor in the Department of Mechanical and Electromechanical Engineering at National Sun Yat-sen University, Kaohsiung, Taiwan. He also worked in the Department of Product Characterization at the Corporate Research and Development Center, Advanced Semiconductor Engineering Inc. (ASE Group), Kaohsiung, Taiwan, where he focused on system-in-package, panel fan-out technology, and 2.5-D integrated circuit product development, including package-level stress and thermal dissipation analysis and board-level structure reliability analysis. His research interests include finite element simulation and analysis of electronic packaging manufacturing processes, microforce testing methods, and IC failure mode analysis, with over ten years of experience in these fields.

Authors:

Jing-Hao Chen National Formosa University
Mengkai Shih National Sun Yat-sen University, Department of Mechanical and Electro-Mechanical Engineering