Session: 03-20-02: Space Manufacturing II

Paper Number: 167155

Impact of Line Edge Roughness on Device Performance: A Review 

This exploratory study reviews existing research on line-edge roughness (LER) and line-width roughness (LWR) in semiconductor manufacturing, focusing on their impact on nanoscale device performance. As Extreme Ultraviolet Lithography (EUVL) enables sub-5 nm patterning, controlling LER is crucial to maintaining device reliability, stabilizing threshold voltage, and reducing leakage current. By synthesizing findings from multiple studies, this review examines the stochastic origins of LER, including photon shot noise and resist material interactions, the transfer of roughness during plasma etching, and its influence on Complementary Metal-Oxide-Semiconductor (CMOS) transistor performance.

This study also examines advancements in metrology and strategies for reducing Line Edge Roughness (LER). It focuses on improved resist formulations and virtual fabrication techniques. The review emphasizes key challenges and potential optimizations by incorporating industry guidelines and performance targets. The advanced research results focused on reducing variability from LER and improving the production of future semiconductor devices.

Method

This study is an exploratory review of existing research on line-edge roughness (LER) and line-width roughness (LWR) in semiconductor manufacturing, focusing on their formation mechanisms and impact on device performance. The study examines the fundamental sources of LER, including photon shot noise and resist material interactions during Extreme Ultraviolet Lithography (EUVL), as well as the role of stochastic effects in pattern formation.

The review further explores metrology techniques for characterizing LER, post-processing techniques for roughness reduction, and the impact of plasma etching on LER transfer. Prior computational modeling approaches evaluate the effect of LER on Complementary Metal-Oxide-Semiconductor (CMOS) transistor performance, including performance targets for EUVL.

Additional studies on industry challenges and process improvements, such as virtual fabrication techniques and optimized resist formulations, are also examined. This synthesis provides insights into strategies for mitigating LER and improving nanoscale semiconductor manufacturing.

Value

This exploratory study consolidates findings from various research efforts to enhance understanding line-edge roughness (LER) and line-width roughness (LWR) in semiconductor manufacturing. Reviewing existing literature provides insights into LER formation mechanisms, including stochastic effects from photon shot noise and resist material interactions, as well as the fundamental principles of LER.

The study examines how LER propagates through plasma etching processes, leading to performance variability in nanoscale CMOS transistors. Computational modeling techniques further assess the impact of LER on device characteristics—and performance metrics outlined in industry guidelines.

Additionally, the review highlights advancements in LER metrology and strategies for roughness mitigation, including post-processing techniques, optimized resist formulations, and virtual fabrication approaches, as well as future insights to improve semiconductor devices, manufacturing processes, and equipment manufacturing.

This study emphasizes the need for continued research into LER control and process optimization to support the development of next-generation semiconductor devices and the semiconductor manufacturing process with equipment improvement.

Presenting Author: Nitish Kumar Singh Rochester Institute of Technology

Presenting Author Biography: I am a first-year graduate student pursuing a Master of Science in Manufacturing and Mechanical System Integration with a minor in Semiconductor Manufacturing. I am dedicated to research and focus on improving device performance through advancements in manufacturing processes and semiconductor equipment optimization.

Authors:

Nitish Kumar Singh Rochester Institute of Technology
Martin K. Anselm Rochester Institute of Technology
Krittika Goyal Rochester Institute of Technology
Intae Whoang SK Hynix
Jun Han Bae Rochester Institute of Technology